1,623 research outputs found

    The communication processor of TUMULT-64

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    Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type, distributed memory, message passing, high performance, real-time and fault tolerant. A distributed real-time operating system has been realized, consisting of a multi-tasking kernel per node, inter process communication via typed messages and a distributed file system. In this paper first a brief description of the system is given, after that the architecture of the communication processor will be discussed. Reduction of the communication overhead due to message passing will be emphasized.\ud \u

    The Sequential Order of Procedural Instructions: Some Formal Methods for Designers of Flow Charts

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    Document designers who present procedural instructions can choose several formats: prose, table, logical tree, or flow chart. In all cases, however, it is essential that the instructions are ordered in a way that allows users to reach the outcome in as little time as possible. In this article two formal methods are discussed that help determine which order is most efficient. The first method is based on the selection principle. The second method is based on the principle of the average least effort

    Throughput of Streaming Applications Running on a Multiprocessor Architecture

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    We study the timing behaviour of streaming applications running on a multiprocessor architecture. Dependencies are derived between the application throughput and the timing characteristics of the processors and communication. Four different processor organizations that strongly influenced the results are considered and compared

    On hardware for generating routes in Kautz digraphs

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    In this paper we present a hardware implementation of an algorithm for generating node disjoint routes in a Kautz network. Kautz networks are based on a family of digraphs described by W.H. Kautz[Kautz 68]. A Kautz network with in-degree and out-degree d has N = dk + dk¿1 nodes (for any cardinals d, k>0). The diameter is at most k, the degree is fixed and independent of the network size. Moreover, it is fault-tolerant, the connectivity is d and the mapping of standard computation graphs such as a linear array, a ring and a tree on a Kautz network is straightforward.\ud The network has a simple routing mechanism, even when nodes or links are faulty. Imase et al. [Imase 86] showed the existence of d node disjoint paths between any pair of vertices. In Smit et al. [Smit 91] an algorithm is described that generates d node disjoint routes between two arbitrary nodes in the network. In this paper we present a simple and fast hardware implementation of this algorithm. It can be realized with standard components (Field Programmable Gate Arrays)

    Comparison of trace metal bioavailabilities in European coastal waters using mussels from Mytilus edulis

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    Mussels from Mytilus edulis complex were used as biomonitors of the trace metals Fe, Mn, Pb, Zn, and Cu at 17 sampling sites to assess the relative bioavailability of metals in coastal waters around the European continent. Because accumulated metal concentrations in a given area can differ temporally, data were corrected for the effect of season before large-scale spatial comparisons were made. The highest concentration of Fe was noted in the North Sea and of Mn in the Baltic. Increased tissue concentrations of Pb were recorded in the mussels from the Bay of Biscay and the Baltic Sea. Low concentrations of metals were determined in the mussels from the Mediterranean Sea and the Northern Baltic. Relatively low geographic variations of Cu and Zn indicate that mussels are able to partially regulate accumulated body concentrations, which means Cu and Zn are, to some extent, independent of environmental concentrations

    DCOS, a Real-Time Light-weight Data Centric Operating System

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    DCOS is a Data Centric lightweight Operating System for embedded devices. Despite limited energy and hardware resources, it supports a data driven architecture with provisions for dynamic loadable Modules. It combines these with Real-Time provisions based on Earliest Deadline First with a simple but smart resource handling mechanism. We will give an overview of the capabilities of DCOS and we will describe the basics of the main mechanisms

    Lightweight EDF scheduling with deadline inheritance

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    EDFI is a lightweight real-time scheduling protocol that combines EDF with deadline inheritance over shared resources. We will show that EDFI is flexible during a tasks admission control, efficient with scheduling and dispatching, and straightforward in feasibility analysis. The application programmer only needs to specify a tasks timing constraints (deadline, period, runtime) and resource needs, after which EDFI can execute admission control, scheduling, dispatching and resource synchronisation automatically. EDFI avoids gratuitous task switching and its programming overhead as well as runtime overhead is very low, which makes it ideal for lightweight and featherweight kernels. We will illustrate the elegance of the underlying theory and we will shortly discuss the implementation of EDFI in three different operating systems

    Architecture Design Space Exploration for Streaming Applications Through Timing Analysis

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    In this paper we compare the maximum achievable throughput of different memory organisations of the processing elements that constitute a multiprocessor system on chip. This is done by modelling the mapping of a task with input and output channels on a processing element as a homogeneous synchronous dataflow graph, and use maximum cycle mean analysis to derive the throughput. In a HiperLAN2 case study we show how these techniques can be used to derive the required clock frequency and communication latencies in order to meet the application's throughput requirement on a multiprocessor system on chip that has one of the investigated memory organisations
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